1. Field of the Invention
The present invention relates to the field of fabrication of integrated circuits, and, more particularly, to a semiconductor device having metal silicide portions formed therein and a method of forming metal silicide portions on silicon-containing regions.
2. Description of the Related Art
Field effect transistors represent the most frequently used circuit elements in modern integrated circuits. Typically, a huge number of field effect transistors is simultaneously formed on an appropriate substrate and are connected to establish the required functionality of the circuit. In presently available integrated circuits, silicon is the primarily used semiconductor material and forms an essential part of a field effect transistor. Generally, a silicon-based field effect transistor comprises two highly doped silicon regions, also referred to as drain and source regions, that are embedded in a lightly and inversely doped silicon region, the so-called n-well or p-well, depending on the type of transistor. The drain and the source regions are spaced apart with a channel region interposed, wherein a conductive channel forms between the drain and source regions in the channel region upon application of an appropriate voltage to a gate electrode that is usually formed over the channel region and is separated therefrom by a gate insulation layer, often provided as a gate oxide layer.
Thus, in the most common field effect transistors, the gate structure essentially comprises the gate electrode formed above the gate insulation layer, with polysilicon often being selected as the material for forming the gate electrode for several reasons. For instance, polysilicon exhibits high compatibility with subsequent high temperature processes. Moreover, the polysilicon interface with thermal silicon dioxide (SiO2) is well understood and electrically stable. Furthermore, polysilicon is more reliable than aluminum gate materials and can be deposited conformally over steep topography.
However, problems arise when polysilicon is used as a gate material, due to its higher resistivity compared to aluminum. In fact, the defects in the grain boundaries of the polysilicon, together with the decreased overall free carrier concentration, cause the resistivity of polysilicon lines, such as the gate electrode, to increase.
In particular, even when doped at the highest practical concentration, a 0.5xcexc thick polysilicon film has a sheet resistance of about 20 xcexa9/sq (compared to 0.05 xcexa9/sq for a 0.5xcexc thick aluminum film). The resulting high values of interconnect line resistance can lead to relatively long RC time constants (i.e., long propagation delays) and severe DC voltage variations within a VLSI (very large scale integration) circuit.
To overcome this drawback, several solutions have been proposed and developed in the art. Among these solutions, the formation of metal silicides on the top of the polysilicon gate structure proved to be the most reliable one for obtaining the lowest resistance values.
A typical prior art method of forming metal silicides on silicon-containing regions, such as the gate electrode, of a CMOS transistor will be described in the following with reference to FIGS. 1a-1d. In FIGS. 1a-1d, reference 1 relates to an arbitrary section of a substrate, for instance a silicon wafer, on which a CMOS transistor 100 is to be formed. In particular, in FIG. 1a, there is depicted the situation at the moment during the manufacturing process when metal silicides are to be formed. Accordingly, in FIG. 1a, reference 2 relates to isolation structures which have been previously formed. These isolation structures 2 divide the section of the substrate 1 into two portions, on which the PMOS transistor and the NMOS transistor are to be formed, respectively. In this particular case, the PMOS portion is depicted on the left side of the figure and the NMOS portion on the right side of the figure.
Moreover, in FIGS. 1a-1d, references 3p and 3n relate to the gate polysilicon electrodes of the PMOS and NMOS transistors, respectively. References 4p and 4n relate to oxide side spacers formed on the sidewalls of the gate polysilicon electrodes. References 6p and 6n relate to the gate insulation layers on the PMOS region and the NMOS region, respectively. Finally, references 5p and 5n relate to the source and drain regions of the PMOS and NMOS transistors, respectively.
Subsequently, in a next step, a metal layer 7 is deposited on the CMOS region 100, as depicted in FIG. 1b. Usually, either titanium (Ti) or cobalt (Co) is used as a metal for forming the metal layer 7, and, typically, a physical vapor deposition (PVD) sputtering process is carried out for depositing the metal layer 7.
Once the metal layer 7 has been deposited, a low temperature thermal step (approximately 450xc2x0 C. or 650xc2x0 C. for cobalt and titanium, respectively) is carried out to react the metal in contact with silicon (Si) on the source/drain regions 5p and 5n and the polysilicon gate electrodes 3p and 3n. During the thermal step, inter-diffusion of the polysilicon and metal occurs, on the upper surface 10p, 10n of the polysilicon gate electrode 3p and 3n as well as on the source/drain regions 5p and 5n not covered by oxide. As a result, metal silicides 8p and 8n are formed, as depicted in FIG. 1c, whereby the metal is at least partially consumed.
In a subsequent step, as depicted in FIG. 1d, the unreacted metal is selectively removed with a selective wet-etch step, leaving behind the metal silicide layers 8p and 8n on top of the polysilicon gate electrodes 3p and 3n and on the source and drain regions 5p and 5n. 
Commonly, a further heat treatment is carried out at a higher temperature than the previous heat treatment to transform the metal silicide 8p, 8n into a more stable phase that exhibits a lower resistance than the metal silicide formed during the previous low temperature heat treatment. For example, if cobalt is used in the first heat treatment, a cobalt monosilicide is formed, which is then converted into a cobalt disilicide.
Since the finally-obtained metal silicide layers 8p and 8n exhibit a sheet resistance which is much lower compared to the sheet resistance of polysilicon, the total resistance of the gate electrodes 3p, 3n including the metal silicide layers 8p, 8n is decreased.
The prior art method described above has accomplished satisfactory results for devices having minimum feature sizes of 0.5xcexc and more. The above method, however, is not completely adequate to compensate for the increase of the polysilicon sheet resistance which arises in cases of deep-sub-micron devices, i.e., with feature sizes smaller or equal to 0.25xcexc. The reason for this can be explained as follows. As a general rule, decreasing the transistor size, i.e., the channel length, in FIG. 1 the horizontal distance between the drain/source regions 5p or between the drain/source region 5n, requires reducing the thickness of the gate insulation layer 6p, 6n and necessitates shallower source/drain regions, which in turn restricts the achievable thickness of the metal silicides 8p, 8n. As the metal silicides 8p, 8n for the gate electrodes 3p, 3n are simultaneously formed with the metal silicides of the drain and source regions, the thickness, and thus the reduction in resistance, of the gate silicide is also restricted.
As the cross-sectional dimensions of the polysilicon gate electrodes decrease as a result of the continuous miniaturization of the devices, the sheet resistance of the polysilicon portions of the gate structures inversely increases and becomes predominant with respect to the low resistance of the silicide layers. The final, total resistance of the gate electrodes is therefore only scarcely influenced by the silicide layer but practically corresponds to the resistance of the polysilicon portion of the gate structure.
Since the trend toward ever decreasing miniaturization of the devices manufacturable on a substrate will continue in years to come, it clearly results that the formation of metal silicide layers on the top of gate polysilicon lines according to the prior art methods will render it very difficult to realize gate structures featuring resistances in conformity with the electrical performances required.
Accordingly, in view of the above explained problems, it would be desirable to improve the resistance of polysilicon lines eliminating or at least partially limiting the drawbacks of the prior art.
In general, the present invention is directed to devices and a method allowing the resistance of polysilicon layers to be significantly reduced by forming an increased silicide region in conductive silicon-containing lines. Moreover, the present invention allows the realization of recessed spacers for the manufacturing of field effect transistors, wherein the side spacers cover only the lower portions of the sidewalls of the gate polysilicon lines.
Additionally, silicide layers may be formed on polysilicon lines of a significantly increased thickness compared to the metal silicide layers formed on the source and drain areas, wherein the PN-junction integrity of the source/drain areas is not compromised.
For this purpose, according to one embodiment, the present invention relates to a method of decreasing the resistance of a conductive silicon-containing feature, wherein the method comprises forming a conductive silicon-containing feature, the feature having sidewalls and an upper surface and forming spacer elements adjacent a portion of the sidewalls, the spacers covering less than all of the sidewalls and defining an exposed portion of the sidewalls. Moreover, the method comprises forming a metal layer on at least the upper surface and exposed portion of the sidewalls, and forming a metal silicide on the upper surface and the exposed portion of the sidewalls by performing at least one thermal treatment.
According to another embodiment, the invention relates to a method of forming the gate electrode of at least one field effect transistor to be formed on a substrate. The method comprises forming at least one line of polysilicon on an active region of the at least one transistor and forming dielectric sidewall spacers on the lower portion of the sidewalls of the at least one polysilicon line by depositing a layer of a dielectric material on the upper surface and the sidewalls of the at least one polysilicon line and etching the dielectric material to expose the upper surface and a portion of the at least one polysilicon line. Furthermore, the method comprises forming a metal layer on the upper surface and the exposed portions of the sidewalls of the at least one polysilicon line, and reacting, at least partially, the polysilicon and the metal at the polysilicon metal interface into metal silicide by a thermal treatment.
In still another embodiment of the present invention, there is provided a field-effect transistor comprising at least one silicon-containing gate electrode. The field effect transistor further comprises a metal silicide layer covering the upper surface and the upper portions of the sidewalls of the at least one silicon-containing gate electrode, wherein the upper portion covers at least 10-50% of the total sidewall area of the silicon-containing gate electrode.